Circuit arrangement for generating a direct control voltage which is dependent on an alternating voltage

ABSTRACT

The invention relates to a circuit arrangement in a compander system for generating a direct control voltage which is dependent on an alternating voltage with the circuit arrangement including a time constant switch. The conductance determining the time constant in a charging current circuit is constantly varied in the transfer range in dependence on the voltage of a charging capacitor when a time constant switch takes place from one fixed value to a second fixed value.

BACKGROUND OF THE INVENTION

The present invention relates to a circuit arrangement for generating adirect control voltage which is dependent on an alternating voltage.More particularly, the present invention relates to such a circuitarrangement, particularly for dynamic compression or expansion,including a first charging capacitor which is charged through a firstcharging circuit and is discharged through a first discharging circuit,and a second charging capacitor which is charged through a secondcharging circuit and a third charging circuit connected in paralleltherewith and is discharged through a second discharging circuit, withthe third charging circuit including a controllable current path whichis actuated when the voltage of the first charging capacitor exceeds agiven threshold value.

German published patent application DE-AS 2,830,784, corresponding toU.S. Pat. No. 4,321,482 issued Mar. 22, 1982 to Ernst Schroder,discloses the use of such a circuit arrangement in compander systems.

For good operation of a compander system it is necessary to have a shortdecay time so that, after an abrupt end of the useful signal, there willbe no noise tails. On the other hand, too short a delay time withlow-frequency useful signals leads to high fluctuations in the controlvoltage and thus to signal distortion through regulation. To avoid suchsignal distortion, a long decay time is required. These contradictoryrequirements are met by time constant switching. Such switching iseffected at the compander end by the alternating voltage output signaland at the expander end by the alternating voltage input signal.

Such charging time constant switching is realized, for example, by aretriggerable monoflop, as disclosed in "Wissenschaftliche BerichteAEG-TELEFUNKEN" [Scientific Reports from AEG-TELEFUNKEN], volume 52(1979), page 103.

In this circuit, a capacitor is charged via a current source. One inputof a differential amplifier is connected with the capacitor, the otherinput with a reference voltage. The charging of the capacitor firstproduces a time delay. If the capacitor voltage finally reaches thelevel of the reference voltage, the differential amplifier is switchedvery quickly. This is done in a range of about 50 mVolt. The switchingof a regulating time constant effected by this circuit therefore occursvery quickly.

This sudden switching of the time constant becomes audible if, due totolerances of the time determining capacitor and/or its chargingcurrent, the switching moments of the time constants in the compressorand the expander no longer coincide.

SUMMARY OF THE INVENTION

It is the object of the present invention to reduce tolerance influencesof the time determining members of the prior art circuit with lowexpenditures.

The above object is achieved by a circuit arrangement for generating adirect control voltage which is dependent on an alternating voltageinput signal, particularly for dynamic compression or expansion,comprising, in combination: an input terminal for an alternating voltageinput signal; a first charging capacitor; a first charging circuit meansfor charging the first capacitor; a first discharging circuit means,controlled by the signal at the input terminal, for discharging thefirst capacitor; a second charging capacitor whose charge voltageconstitutes the control voltage; a second charging circuit for chargingthe second capacitor; a second discharging circuit means, controlled bythe signal at the input terminal, for discharging the second capacitor;a third charging circuit means, connected in parallel with the secondcharging circuit means, for charging the second capacitor, with thethird charging circuit means including a controllable current path whichis actuated when the voltage of the first charging capacitor exceeds agiven threshold value; and further circuit means for causing thecharging current of the third charging circuit means to have a firstcurrent value at a voltage across the first charging capacitor below thethreshold value and a second value when the capacitor voltage is abovethe threshold value with the first or second value being proportional tothe voltage of the first charging capacitor up to a limit value, andwith the range of the first value immediately following the range of thesecond value.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic circuit diagram of one embodiment of the circuitaccording to the invention.

FIG. 2 is a schematic circuit diagram of another embodiment of thecircuit according to the invention.

FIG. 3 shows time diagrams for the current or voltage which are used toexplain the invention, with:

FIG. 3a showing the curve of a signal voltage across terminal 1;

FIG. 3b showing the capacitor voltage of capacitor 7;

FIG. 3c showing the current curve through the transistor 21; and

FIG. 3d showing the curve of the control voltage across terminal 2.

FIG. 4 is a schematic circuit diagram showing a still further embodimentof the circuit according to the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows the configuration of a circuit according to the invention.The circuit includes an input 1 for the low frequency alternatingvoltage U_(NF) and an output 2 for the direct control voltage U_(ST).The signal at input 1 controls, via a voltage divider 4, 40, the base oftransistors 5 and 6 which are connected as a Darlington circuit. Theemitter of transistor 6 is connected to reference potential as is theother end of voltage divider 4, 40. The collectors of transistors 5 and6 are connected together and with the common connection of one terminalof a current source 3, a charging capacitor 7, a diode path 15-20containing six diodes, and the base of a transistor 21. The capacitor 7and the diode path 15-20 have their second or opposite terminalsconnected to reference potential.

Transistor 21 and transistor 24 together form a differential amplifier.The emitter of transistor 21 is connected, via a feedback resistor 22,with the emitter of transistor 24 and with one terminal of a currentsource 23, whose second or opposite terminal is connected to referencepotential. The collector of transistor 24 is connected to the operatingvoltage U_(b). The base of transistor 24 is connected to the commonconnection of a diode path 26-28 containing three diodes, and a currentsource 25. The second terminal of the diode path 26-28 is connected toreference potential, while the second terminal of the current source 25is connected to the reference voltage U_(b). The collector of transistor21 is connected with the base of a transistor 11 and additionally, viathe series connection of a diode 13 and a resistor 12, with theoperating voltage U_(b). The emitter of transistor 11 is connected tothe operating voltage U_(b) via a resistor 10. The collector oftransistor 11 leads to the common point of connection of the output 2, asecond charging capacitor 8, a resistor 9 and the collector of atransistor 41. The second terminal or contact of capacitor 8 isconnected to reference potential and the other terminal of resistor 9 isconnected to the operating voltage U_(b) so that the capacitor 8 ischarged by the operating voltage via resistor 9. Transistor 41 has itsemitter connected to reference potential and its base connected via afurther voltage divider 42, 43 to the input 1, whereby transistor 41 iscontrolled by the low frequency signal at input 1.

Transistors 5, 6 and transistor 41 each represent a respective thresholdcircuit. If the input voltage at input 1 exceeds a threshold set by thebase-emitter voltage of transistor 41 and the voltage divider 43, 42,the collector-emitter path of transistor 41 becomes conductive. As aresult, capacitor 8 is discharged toward more negative values via thecollector-emitter resistance of transistor 41, and the output voltage atterminal 2 becomes more negative. If the input voltage drops back tobelow this threshold value, transistor 41 is blocked again and capacitor8 is charged again toward more positive values via resistor 9, and thusthe output voltage at output 2 becomes more positive.

In this respect, components 8, 9, 41, 42 constitute a fast rectifiercircuit as it is disclosed in German Patent No. 2,406,258, FIG. 12 andGerman allowed application DE-AS 2,403,799, FIG. 2, both correspondingto U.S. Pat. No. 3,969,680 issued July 13, 1976.

The remaining threshold switch or circuit comprised of transistors 5, 6and voltage divider 4, 40 acts as a discharge current path connected inparallel to capacitor 7. If a signal is present at input 1, which signalis greater than the threshold value of the arrangement 4, 40, 5, 6, thecapacitor 7 is quickly discharged via transistor 6 down to a residualvoltage of approximately one diode voltage. This results in the voltageacross the base of the transistor 24 being higher by two diode voltagesthan the voltage across the base of transistor 21. The transistor 21 isthus blocked, its collector current I₂₁ is zero and so is the outputcurrent I₁₁ of the current mirror circuit 10, 11, 12, 13. Therefore,only the charging current through resistor 9 is effective in chargingcapacitor 8. The large time constant results from the product ofcapacitor 8 and resistor 9. If the signal at input 1 falls below thethreshold voltage of the arrangement 4, 40, 5, 6, the Darlington circuit5, 6, is blocked. The capacitor voltage of capacitor 7 then increaseslinearly, originating from the current source 3, from one diode voltageto a value limited by the six diodes 15-20. The time which expires untilthe capacitor 7, and thus the base of transistor 21, reaches three diodevoltages, i.e. the same voltage as the base of transistor 24, is thedelay time or holding time of the circuit. When this voltage is reachedat the base of transistor 21, it continuously takes over the current I₂₃from current source 23, until the current I₂₃ is taken over completelyby transistor 21, e.g. at 5 diode voltages, and transistor 24 blocks.The voltage transfer range is equal to the product of the feedbackresistance 22 and current I₂₃. The current transfer to transistor 21 isproportional to the capacitor voltage of capacitor 7. The time for thecurrent transfer lies in the order of magnitude of the time delay of thecircuit. At the same time, the rise of current I₂₁ in transistor 21 issupplied to capacitor 8 as current I₁₁ by the current mirror circuitcomprising resistors 10 and 12, diode 13 and transistor 11. Current I₁₁is set according to I_(11max) =I₂₃ ·R₁₂ /R₁₀. The constantly risingcurrent I₁₁, in contradistinction to that in German publishedapplication DE-AS 2,830,784, corresponding to U.S. Pat. No. 4,321,482,causes the course of the control voltage at output 2 to become morecurved or rounder.

FIG. 2 shows another embodiment of the circuit according to theinvention. This circuit differs from that of FIG. 1 in that the feedbackresistor 22 is omitted, and a feedback resistor 38 is provided in theemitter branch or path of transistor 24. Moreover, the diode path 26-28of FIG. 1 is replaced by a diode path 33-37 containing five diodes.

In this circuit, current transfer begins at transistor 21, if its basevoltage reaches a value which corresponds to the base voltage oftransistor 24 minus the voltage I₂₃ ·R₃₈ which results due to currentI₂₃ flowing through resistor 38. The current transfer range correspondsto the product of I₂₃ ·R₃₈.

In both described embodiments, the diode path 15-20 at the base oftransistor 21 may be replaced by a corresponding Zener diode since thisdiode path serves only to limit the voltage across capacitor 7 above avalue which is required for the full current takeover by transistor 21.The diode path 15-20 may also be omitted, in which case the voltageacross the capacitor rises up to the operating voltage U_(b).

Diode paths 26-28 and 33-37 and the current source 25 can likewise bereplaced by other suitable circuits which generate an essentiallyconstant voltage across the base of transistor 24.

In the operation of the described circuit, if the signal, which beginsat t=T_(O) as shown in FIG. 3a, present at input 1 is greater than thethreshold voltage of the arrangement 4, 5, 6, 40, the Darlington circuit5, 6 becomes conductive during the signal duration. As shown in FIG. 3b,the capacitor voltage U₇, which had been at its maximum value of sixdiode voltages (6U_(b)), is immediately discharged to about one diodevoltage. The current through transistor 21, according to FIG. 3c,therefore becomes zero. If the voltage of FIG. 3a also exceeds thethreshold value of the arrangement 41, 42, 43, capacitor 8 is likewisedischarged and, as shown in FIG. 3d, the control voltage U_(ST) atoutput 2 has its minimum value. If the signal U_(NF) at input 1 becomeszero or drops to below the respective threshold voltages, transistors 5,6, and 41 are blocked. As shown in FIG. 3b, the capacitor voltage U₇then rises continuously to the value limited by diodes 15-20, i.e.6U_(D). As can be seen in FIG. 3c, the current I₂₁ begins to flow assoon as the capacitor voltage U₇ has reached the value of three diodevoltages. Thereafter, the current I₂₁ then increases proportionally tothe capacitor voltage U₇ from zero to its maximum value. The resultingvoltage curve at output 2 is shown in FIG. 3d. During the holding timeof the circuit, i.e. until the current I₂₁ begins to flow, the controlvoltage U_(ST) increases slowly. The rise is determined by the largetime constant formed of capacitor 8 and resistor 9. After the holdingtime, the control voltage U_(ST) becomes rounder. The constantlyincreasing current I₁₁, which is generated by the current mirror circuitfrom current I₂₁, is superposed on the current supplied to capacitor 8through resistor 9. Thus the constantly rising current I₁₁ produces acurved, i.e. rounded, rise in the control voltage which increases to itsmaximum value. If the control voltage U_(ST) is generated in thismanner, two rounded curves are now displaced with respect to one anotheras a result of the above-mentioned tolerance influences. The influenceof this shift is smaller on the average than in the prior art circuit.

FIG. 4 shows a further embodiment of the invention which is used as aperipheral circuit for the known HIGH-COM IC U401B, manufactured byAEG-Telefunken, Heilbronn, West-Germany here marked with the referencenumeral 61, and which also causes the control voltage U_(ST) to berounded. One terminal 44 of the IC 61, at which the operating voltageU_(b) is present, is connected to the emitter of a transistor 52, via aresistor 12 to the emitter of a transistor 54, via a resistor 10 to theemitter of transistor 11, and to one terminal of a resistor 9. Thesecond terminal of resistor 9 is connected to the collector oftransistor 11, one terminal of charging capacitor 8, and an outputterminal 46 of the IC 61. The other terminal of charging capacitor 8 isconnected to the reference potential. Output terminal 45 of the IC 61 isconnected with the base of a transistor 52 and with one terminal of aresistor 49. The other terminal of resistor 49 is connected to referencepotential and to the common connecting point of one terminal of aresistor 50 and a capacitor 51. The resistor 50 and the capacitor 51form a parallel circuit whose other common connection point is connectedwith the collector of transistor 52, the base of transistor 54, thecollector of transistor 54, and the base of transistor 11. Terminal 47of the IC 61 is connected to reference potential.

Terminals 44 and 45 of the IC 61 have an internal switch 53 which iscontrolled by the signal voltage U_(NF). If a signal voltage U_(NF) ispresent, switch 53 is open; if the signal voltage U_(NF) drops below athreshold value (see German published application DE-AS 2,850,736corresponding to U.S. Pat. No. 4,318,009, issued Mar. 2, 1982 to ErnstSchroder), switch 53 is closed with a time delay which is effected by acircuit element in IC 61 (see Wissenschaftliche Berichte, AEG-Telefunken52 (1979) 1-2, page 103). Equivalently to the preceding embodiments, theinternal circuitry of the IC 61 includes the voltage divider resistors42, 43 and the transistor 41 connected between the input terminal forvoltage U_(NF) and the terminals 46 and 47. The control voltage U_(ST)is present at terminal 46 of IC 61.

With the circuit of FIG. 4, if a signal U_(NF) is present, switch 53 isopen. This causes transistor 52 to conduct and charge capacitor 51 tothe operating voltage +U_(b) at terminal 44. Transistor 11 is blocked,and no current flows through resistor 10 and transistor 11 to capacitor8. If the signal U_(NF) is no longer present, switch 53 is closed with atime delay and thus transistor 52 is blocked as well. Capacitor 51 nowdischarges slowly through resistor 50. The reduction of the voltageacross the base of transistor 54 causes the latter to become conductivegradually and a constantly increasing current flows through resistor 50to ground. In the equilibrium state, a voltage develops across capacitor51 which is determined by the current flowing through resistor 12,transistor 54 and resistor 50. The current, which increases until theequilibrium state is reached, is supplied to capacitor 8 by the currentmirror circuit 10, 11, 12, 54. The voltage present across capacitor 8corresponds to the control voltage U_(ST). The discharging circuit ofcapacitor 8, including the voltage divider 43, 42 and transistor 41, isset so that it is actuated by the peaks of the signal. Capacitor 8 ischarged constantly by the current given by resistor 9.

It will be understood that the above description of the presentinvention is susceptible to various modifications, changes andadaptations, and the same are intended to be comprehended within themeaning and range of equivalents of the appended claims.

What is claimed is:
 1. A circuit arrangement for generating a directcontrol voltage which is dependent on an alternating voltage inputsignal, particularly for dynamic compression or expansion, said circuitarrangement comprising, in combination: an input terminal for analternating voltage input signal; a first charging capacitor; a firstcharging circuit means for charging said first capacitor; a firstdischarging circuit means, controlled by the signal at said inputterminal, for discharging said first capacitor; a second chargingcapacitor whose charge voltage constitutes said control voltage; asecond charging circuit for charging said second capacitor; a seconddischarging circuit means,controlled by the signal at said inputterminal, for discharging said second capacitor; a third chargingcircuit means, connected in parallel with said second charging circuitmeans, for charging said second capacitor, said third charging circuitmeans including a controllable current path which is actuated when thevoltage of said first charging capacitor exceeds a given threshold valueand further circuit means for causing the charging current of said thirdcharging circuit means to have a first current value at a voltage acrosssaid first charging capacitor below said threshold value and a secondvalue when said voltage is above said threshold value with said first orsecond value being proportional to the voltage of said first chargingcapacitor up to a limit value, and with the range of said first valueimmediately following the range of said second value.
 2. A circuitarrangement as defined in claim 1, wherein said third charging circuitforms a first branch in a current mirror circuit whose second branch isincluded in said further circuit means;and wherein the current in saidsecond branch of said current mirror circuit is determined by themagnitude of the voltage of said first charging capacitor.
 3. A circuitarrangement as defined in claim 2, wherein said further circuit meansincludes a feedback connected amplifier through which said current ofsaid second branch of said current mirror circuit is conducted.
 4. Acircuit arrangement as defined in claim 3 wherein said amplifier is adifferential amplifier having a first and a second transistor.
 5. Acircuit arrangement as defined in claim 4, wherein said second branch ofsaid current mirror circuit forms the collector circuit of said firsttransistor of said differential amplifier; and the base of said firsttransistor is connected with said first charging capacitor.
 6. A circuitarrangement as defined in claim 4, wherein the emitters of both saidfirst and second transistors of said differential amplifier areconnected together via a resistor.
 7. A circuit arrangement as definedin claim 6, wherein the emitter of one of said first and secondtransistors is connected to ground via a current source.
 8. A circuitarrangement as defined in claim 4, wherein the transfer value of therange of said first current value to the range of said second value ofthe charging current of said third charging circuit is determined by thebias across the base of said second transistor of said differentialamplifier.
 9. A circuit arrangement as defined in claim 1 furthercomprising a limiting circuit connected to said first charging capacitorto limit the voltage of said first charging capacitor.
 10. A circuitarrangement as defined in claim l, wherein the charging current of saidthird charging circuit means below said threshold value of the voltageacross said first charging capacitor is almost zero.
 11. A circuitarrangement as defined in claim 1, wherein the charging current of saidthird charging circuit means above said threshold value of the voltageacross said first charging capacitor is almost zero.